In order to increase the throughput of my VLIW microprocessor in video applications, I analyze the performance under real workloads and find out where to work on. I think SMT (Simultaneous Multithreading) technology will be an efficient method in area and power, considering the features of video compression such as lots of vector operations and high thread-level parallelism. 

Register file is a crucial unit in microprocessor which has register-to-register ISA (Instruction Set Architecture). Multi-ports and high frequency of register file can support the high performance of the whole system. My task is from the design of scheme and layout to the analysis of performance. The tools I utilize are Spice, CosmosSE, CosmosLE, Nanosim, StarRCXT, etc. It has been done well.

The microprocessor is funded by a national project. It is designed in 0.18μm CMOS technology. It includes over one million gates with the speed up to 266MHz. My tasks in this project include:
  * Design of decoder and pipeline controller in VerilogHDL;
  * Verification of the CPU core and SIMD coprocessor, as a manager of 4-person group;
The tools we use include Modelsim, VCS, Design-Compiler, Formality, etc. In the phase of verification, I designed some kernel assembly programs for simulation and built up an efficient test-bench to shorten the verification period. The chip got one-pass and ran MPEG-2 application as we expected.

The register file is designed as a small IP core. It is designed in 0.18um. I design the scheme and finish the layout and optimization. The tools I use are Spice, CosmosSE, Enterprise, Star_sim, StarRC, etc.

The multiplier generator is a research work. It can produce the RTL code under any parameter just like a small EDA tool. I design it in C++ language and synthesize all multipliers of all widths to get the timing and area reports in Design_Compiler.