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Education:
| 5/2002-present |
The University of Texas at Dallas,
Richardson, TX
Ph.D. Candidate in Electrical Engineering
(Microelectronic Circuits
and System).
Thesis title: Synchronization for High-Speed Data
Transmission
Research Projects:
- Multiphase Clock Generator Using a New Delay
Compensation Technique for Clock/Data
Recovery
Description: Designed and simulated a 1GHz 8-phase clock
generator using a new delay compensation technique. It can
generate 8 precisely spaced clocks. This project is a part of
“A 16GHz 1/8 Rate Clock and Data Recovery Circuit”. The
8 phases clocks will be used for sampling the input data of the
clock and data recovery circuit. The process used in this design
is 0.18µm TSMC CMOS technology.
Tools: Cadence (Analog Artist Simulator, Virtuoso).
- A 1GHz Phase-Locked Loop
Description: Designed and simulated a 1GHz phase-locked loop
using self-biasing technique. This project fabricated as a chip.
The process used in this project is 0.25µm TSMC CMOS
technology.
Tools: Cadence (Analog Artist Simulator, Virtuoso)
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| 1/2001-5/2003 |
The University of Texas at Dallas,
Richardson, TX
Master of Science, Electrical Engineering, with an emphasis in
Microelectronic Circuits and System
Research Projects:
Digit circuit design for “8x8 and 16x16 2’s
complement Multiplier Analysis of Microprocessor of TMS320C6x DSP Two-stage Operational Amplifier Design Phase-locked Loop Design
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| 9/1988-7/1992 |
Shandong University, Jinan, Shandong,
P.R.China
Bachelor of Science, Electronics Engineering, with an
emphasis in Electronic & Information System
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| Working Experience |
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| 7/1992-12/2000 |
Jinan Polytechnic College, Jinan, Shandong, P.R.China.
Lecturer, Department of Mechanical & Electrical Engineering.
Taught three courses: Digital Circuit, Microcomputer Theory
and Application, Analog Circuit
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| Computer Skills |
Programming Language: Assembly language (80x86,
MCS-51), C
CAD Tools: Cadence, Magic CAD, Matlab
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