If data are not stored or loaded carefully, memory access may become a dominant factor of performance. Since memory hierarchy is commonly used in practice, such as on-chip cache or memory (local memory) and off-chip memory (remote memory), techniques need to be developed to maximally use on-chip memory for data access. We proposed a problem, data scheduling, which is the problem to decide when and where to store or load data in an optimal way. A technique called carrot-hole data scheduling was developed. Partitioning and execution scheduling are also two key steps applied to optimally store and load data so that local memory misses is minimized. Two journal papers were published.
We also developed a new technique, called multi-dimensional interleaving which consists of a multi-dimensional expansion and compression of the iteration space, followed by a multi-dimensional retiming, while considering memory requirements. Results were published in the papers including one journal paper and three conference papers. It guarantees that all functional elements of a circuitry can be executed simultaneously, and no additional memory queues proportional to the problem size are required.