Dr. Edwin Sha's research interests include Parallel processing and architectures, CAD for application-specific parallel and pipelined architectures, Embedded systems, Data scheduling and partitioning for parallel systems, Loop transformations and parallelizations, Software tools for parallel and distributed systems, VLSI processor arrays, Hardware and Software co-designs. His main research objective is to derive methodologies and optimization techniques for designing reliable and time-and-memory efficient systems. His research on time-and-memory optimization for computation-intensive applications has produced significant results, which solved several important problems. For example, one of his results shows how to find the rate-optimal schedule for general cyclic data-flow graphs on various models and pipeline and non-pipeline styles in polynomial time.
His another research result on timing and memory optimization for multi-dimensional (MD) applications, including satellite image processing, fluid dynamics simulations, and DSP systems, starts a new direction of research area. Several optimization algorithms have been developed such as MD retiming, MD rotation, MD interleaving, Push-up scheduling, communication-sensitive scheduling, and carrot-hole data scheduling and partitioning. One of his results shows that any uniform nested loops can be transformed and parallelized such that the codes in loop body are executed in a fully parallel way. This is a fundamental result and can be applied to applications executed on VLIW or superscalar types of VLSI architectures. He is also investigating design optimization techniques for applications with conditional branches, low-power requirement, and fuzzy or probabilistic uncertainties. New techniques such as branch anticipation, low-power scheduling, probabilistic retiming, probabilistic loop pipelining, and fuzzy scheduling were recently developed. In the PetaFlop Computing Design project, he is designing new techniques to reduce routing congestion, and optimal data placement/movement for Processor-In-Memory arrays, and systems with deep memory hierarchy.
He has published more than 100 papers and graduated 5 Ph.D. students in the past 7 years. Currently he is advising 7 Ph.D. students. He would like to continue to work with students on the areas described above. He is actively participating in professional activities. He has been served as an editor for several journals such as IEEE Transactions on Signal Processing. In 1994, He served as the Program Committee Chair for the Fourth IEEE Great Lakes Symposium on VLSI. He also served as program committee in numerous conferences such as International Symposium on System Synthesis, International Conference on Parallel and Distributed Computing and Systems, and International Symposium on the Frontiers of Massively Parallel Computation, etc. He received Oak Ridge Association Junior Faculty Enhancement Award in 1994, and NSF CAREER Award in 1995 in the area of Design, Tools and Test. He was a guest editor for the special issue on Low Power Design of IEEE Transactions on VLSI Systems in 1997. He is also serving as the program chair for the International Conference on Parallel and Distributed Computing Systems (PDCS 2000), Las Vegas, August 2000.