SRAM Circuit Diagrams

Professor C. D. Cantrell

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Please note that these circuit diagrams are copyright (c) 1997 by C. D. Cantrell. All rights reserved.

Writing to row 3 of a 4Xn SRAM. Note that the row is addressed through a decoder and that the output of the decoder is disabled unless the chip select signal is asserted. Also note that each SRAM cell is a D latch with read enable and write enable signals.

Reading from row 3 of a 4Xn SRAM. Note that the read enable signal is asserted. The data signals are actually "don't cares" because the write enable signal is deasserted.